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 PRELIMINARY DATASHEET
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER ICS291 Description
The ICS291 field programmable spread spectrum clock synthesizer generates up to six high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency crystal input. It is designed to replace crystals, crystal oscillators and stand alone spread spectrum devices in most electronic systems. Using ICS' VersaClockTM software to configure PLLs and outputs, the ICS291 contains a One-Time Programmable (OTP) ROM for field programmability. Programming features include input/output frequencies, spread spectrum amount, eight selectable configuration registers and up to two sets of three low-skew outputs. Each of the two output groups are powered by a separate VDDO voltage. VDDO may vary from 1.8 V to VDD. Using Phase-Locked Loop (PLL) techniques, the device runs from a standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving board space and cost. The ICS291 is also available in factory programmed custom versions for high-volume applications.
Features
* * * * * * * * * * * * * *
Packaged as 20-pin TSSOP Eight addressable registers Replaces multiple crystals and oscillators Output frequencies up to 200 MHz at 3.3 V Configurable Spread Spectrum Modulation Input crystal frequency of 5 to 27 MHz Clock input frequency of 3 to 166 MHz Up to six reference outputs Separate 1.8 to 3.3 V VDDO output level controls for each bank of 3 outputs Up to two sets of three low-skew outputs Operating voltages of 3.3 V Controllable output drive levels Advanced, low-power CMOS process Available in Pb (lead) free packaging
Block Diagram
VDD PLL1 with Spread Spectrum Divide Logic and Output Enable Control 3 VDDO1
S2:S0
3
OTP ROM with PLL Values
CLK1 CLK2 CLK3
PLL2
CLK4 CLK5 CLK6
PLL3 X1/ICLK Crystal or Clock Input Crystal Oscillator X2 External capacitors are required with a crystal input. 3
GND
PDTS
VDDO2
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Pin Assignment
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
GND S0 S1 VDD VDDO1 CLK1 CLK2 CLK3 GND X1/ICLK
S2 VDD PDTS GND CLK6 CLK5 CLK4 VDDO2 VDD X2
20 pin (173 mil) TSSOP
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Name
GND S0 S1 VDD VDDO1 CLK1 CLK2 CLK3 GND X1/ICLK X2 VDD VDDO2 CLK4 CLK5 CLK6 GND PDTS VDD S2
Pin Type
Power Input Input Power Power Output Output Output Power XI XO Power Power Output Output Output Power Input Power Input Connect to ground.
Pin Description
Select pin 0. Internal pull-up resistor. Select pin 1. Internal pull-up resistor. Connect to +3.3 V. Power supply for outputs CLK1-CLK3. Output clock 1. Weak internal pull-down when tri-state. Output clock 2. Weak internal pull-down when tri-state. Output clock 3. Weak internal pull-down when tri-state. Connect to ground. Crystal input. Connect this pin to a crystal or external input clock. Crystal Output. Connect this pin to a crystal. Float for clock input. Connect to +3.3 V. Power supply for outputs CLK4-CLK6. Output clock 4. Weak internal pull-down when tri-state. Output clock 5. Weak internal pull-down when tri-state. Output clock 6. Weak internal pull-down when tri-state. Connect to ground. Power-down tri-state. Powers down entire chip and tri-states clock outputs when low. Internal pull-up resistor. Connect to +3.3 V. Select pin 2. Internal pull-up resistor.
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External Components
The ICS291 requires a minimum number of external components for proper operation.
The ICS291 also provides separate output divide values, from 2 through 63, to allow the two output clock banks to support widely differing frequency values from the same PLL. Each output frequency can be represented as:
OutputFreq
Series Termination Resistor
Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20 .
=
REFFreq
M ---N
Output Drive Control
The ICS291 has two output drive settings. For VDDO=VDD, low drive should be selected when outputs are less than 100 MHz. High drive should be selected when outputs are greater than 100 MHz. For VDDO<2.8 V, high drive should be selected for all output frequencies. (Consult the AC Electrical Characteristics for output rise and fall times for each drive option.)
Decoupling Capacitors
As with any high-performance mixed-signal IC, the ICS291 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias on the decoupling circuit.
Crystal Load Capacitors
The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20.
ICS VersaClock Software
ICS applies years of PLL optimization experience into a user friendly software that accepts the user's target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. The user does not need to have prior PLL experience or determine the optimal VCO frequency to support multiple output frequencies. VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate output accuracy, performance trade-off scenarios in seconds.
Spread Spectrum Modulation
The ICS291 utilizes frequency modulation (FM) to distribute energy over a range of frequencies. By modulating the output clock frequencies, the device effectively lowers energy across a broader range of frequencies; thus, lowering a system's electromagnetic interference (EMI). The modulation rate is the time from transitioning from a minimum frequency to a maximum frequency and then back to the minimum.
ICS291 Configuration Capabilities
The architecture of the ICS291 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. The frequency multiplier PLL provides a high degree of precision. The M/N values (the multiplier/divide values available to generate the target VCO frequency) can be set within the range of M = 1 to 1024 and N = 1 to 32,895.
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Spread Spectrum Modulation can be applied as either "center spread" or "down spread". During center spread modulation, the deviation from the target frequency is equal in the positive and negative directions. The effective average frequency is equal to the target frequency. In applications where the clock is driving a component with a maximum frequency rating, down spread should be applied. In this case, the maximum frequency, including modulation, is the target frequency. The effective average frequency is less than the target frequency. The ICS291 operates in both center spread and down spread modes. For center spread, the frequency can be modulated between 0.125% to 2.0%. For down spread, the frequency can be modulated between -0.25% to -4.0%.
Both output frequency banks will utilize identical spread spectrum percentage deviations and modulation rates, if a common VCO frequency can be identified.
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to the output clock frequency may occur at a variety of rates. For applications requiring the driving of "down-circuit" PLLs, Zero Delay Buffers, or those adhering to PCI standards, the spread spectrum modulation rate should be set to 30-33 kHz. For other applications, a 120 kHz modulation option is available.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS291. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Parameter
Supply Voltage, VDD Inputs Clock Outputs Storage Temperature Soldering Temperature Junction Temperature
Condition
Referenced to GND Referenced to GND Referenced to GND Max 10 seconds
Min.
-0.5 -0.5 -65
Typ.
Max.
7 VDD+0.5 VDD+0.5 150 260 125
Units
V V V C C C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (ICS291GP) Ambient Operating Temperature (ICS291GIP) Power Supply Voltage (measured in respect to GND) Power Supply Ramp Time
Min.
0 -40 +3.135
Typ.
Max.
+70 +85
Units
C C V ms
+3.3
+3.465 4
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DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85 C
Parameter
Operating Voltage VDDO Voltage
Symbol
VDD
Conditions
VDDO1 and VDDO2 Config. Dependent - See VersaClockTM Estimates
Min.
3.135 1.80
Typ.
Max.
3.465 VDD
Units
V V mA
Operating Supply Current
IDD
Six 33.3333 MHz outs, VDD=VDDO=3.3 V; PDTS = 1, no load, Note 1 PDTS = 0, no load S2:S0 S2:S0 VDD-0.5 VDD/2+1
25
mA
500 0.4 0.4
Input High Voltage Input Low Voltage Input High Voltage, PDTS Input Low Voltage, PDTS Input High Voltage Input Low Voltage Output High Voltage (CMOS High) Output High Voltage Output Low Voltage Short Circuit Current Nom. Output Impedance Internal Pull-up Resistor Internal Pull-down Resistor Input Capacitance
VIH VIL VIH VIL VIH VIL VOH VOH VOL IOS ZO RPUS RPD CIN
A V V V V V VDD/2-1 V V V 0.4 V
ICLK ICLK IOH = -4 mA IOH = -8 mA (Low Drive); IOH = -12 mA (High Drive) IOL = 8 mA (Low Drive); IOL = 12 mA (High Drive) Low Drive High Drive S2:S0, PDTS CLK outputs Inputs
VDD/2+1 VDD-0.4 2.4 VDDO-0.4
40 70 20 190 120 4 mA k k pF
Note 1: Example with 25 MHz crystal input with six outputs of 33.3 MHz, no load, and VDD = 3.3 V.
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AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85 C
Parameter
Input Frequency Output Frequency Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time
Symbol
FIN
Conditions
Fundamental crystal Clock input VDDO=VDD 1.8 VMin.
5 3 0.314 0.314
Typ.
Max. Units
27 166 200 150 MHz MHz MHz MHz ns ns ns
tOF tOF tOF
80% to 20%, high drive, Note 1 80% to 20%, low drive, Note 1 80% to 20%, high drive, 1.8 V1.0 2.0 2.0
Duty Cycle Output Frequency Synthesis Error Power-up time
49-51 TBD 4 0.6
60 10 2
% ppm ms ms
4
7
ms
One Sigma Clock Period Jitter Maximum Absolute Jitter Pin-to-Pin Skew Note 1: Measured with 15 pF load. tja
Configuration Dependent Deviation from Mean. Configuration Dependent Low Skew Outputs -250
50 +200 250
ps ps ps
Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%.
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
93 78 65 20
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
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Marking Diagrams
20 11
Marking Diagrams (Pb free)
20 11
###### YYWW$$ 291PG
1 20 10 11 1 20
###### YYWW 291PGL
10 11
###### YYWW$$ 291PGI
1 10 1
###### YYWW 291PGIL
10
Notes: 1. ###### is the lot number. 2. YYWW is the last two digits of the year and week that the part was assembled. 3. "I" denotes industrial temperature range (if applicable). 4. "L" denotes Pb (lead) free package. 5. Bottom marking: country of origin.
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Package Outline and Package Dimensions (20-pin TSSOP, 173 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
24
Millimeters Symbol
E1 E
Inches Min Max
Min
Max
INDEX AREA
12 D
A A1 A2 b C D E E1 e L
-- 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 6.40 6.60 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8
-- .047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.252 0.260 0.252 BASIC 0.169 0.177 0.0256 Basic .018 .030 0 8
A2 A1
A c
- Ce
b SEATING PLANE
.10 (.004)
C
L
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Ordering Information
Part / Order Number
291PG 291PGI 291PGLF 291PGILF 291G-XX 291GI-XX 291G-XXLF 291GI-XXLF 291G-XXT 291GI-XXT 291G-XXLFT 291GI-XXLFT 291G-XX 291GIXX 291GXXL 291GIXXL 291G-XX 291GIXX 291GXXL 291GIXXL See page 7
Marking
Shipping Packaging
Tubes Tubes Tubes Tubes Tubes Tubes Tubes Tubes Tape and Reel Tape and Reel Tape and Reel Tape and Reel
Package
20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP
Temperature
0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. The 291G-XX, 291G-XXLF, 291GI-XX, and 291GI-XXLF are factory programmed versions of the 291PG, 291PGLF, 291PGI, and 291PGILF. A unique "-XX" suffix is assigned by the factory for each custom configuration, and a separate data sheet is kept on file. For more information on custom part numbers programmed at the factory, please contact your local IDT sales and marketing representative. While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. VersaClockTM is a trademark of Integrated Circuit Systems, Inc. All rights reserved.
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www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
For Tech Support
408-284-4522 www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc. www.idt.com
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA


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